1. Field of the Invention
The present invention relates generally to an electrically rewritable non-volatile semiconductor memory device such as electrically erasable programmable read only memory (EEPROM). More particularly but not exclusively, this invention relates to a “flash” memory of a NAND type.
2. Description of Related Art
Flash memories are designed to store as data different threshold voltage states of a memory cell (memory transistor) in a way pursuant to the amount of electrical charge of a floating gate thereof. For example, a flash memory stores a negative threshold state as a bit of logic “1” data and stores a positive threshold state as a logic “0” data bit. Data rewriting (erasure and write), also known as reprogramming, is performed by electrically changing the charge amount of the floating gate of a memory cell.
Currently available flash memories include a flash memory chip of the NAND type. In this NAND flash memory, a plurality of memory cells are connected in series together to constitute a NAND string (cell unit). The NAND string has its one terminate end which is connected to a bit line through a first select gate transistor and the other end which is connected to a source line via a second select gate transistor. The multiple memory cells within the NAND string are such that adjacent ones commonly have or “share” a source or drain diffusion layer therebetween. Thus it is possible to make the ratio of a region of a select gate transistor or a contact portion to a single memory cell smaller than that of NOR type flash memories. This leads to achievement of flash memories with higher integration densities.
Controlling memory cells other than a selected memory cell in a NAND string to serve as a current flow path during writing or reading sessions, it is possible to selectively perform writing or reading of a memory cell within the NAND string. A general approach to doing erasure to as follows; all of the memory cells within the NAND string are selected simultaneously and then erased together at a time.
More concretely explaining, a group of memory cells arranged in the direction of a word line constitutes either a single page or two pages, while a group of NAND strings arranged in the direction of word lines makes up a block. And, data read or data write is performed by a page; and data erase by a block.
Although NAND flash memories are capable of lessening the size of a NAND string per se by reducing a minimum device feature size, it is unlikely that select gate transistors and contact portions are shrinkable in a way simply proportional to their microfabrication sizes. To solve this problem, a technique has been proposed for improving the wiring structures of select gate transistors to thereby achieve further increased densities of NAND flash memories. This approach is disclosed, for example, in Published Japanese Patent Application No. 2002-26153 (JP-A-2002-26153).
On the other hand, when an attempt is made to maintain the high integration density of a flash memory by increasing the number of those memory cells making up a NAND string, the unit of data erasure becomes larger, resulting in a decrease in usability. Regarding this point, a technique has been proposed for performing data erase on a per-page basis or alternatively in units of sub-blocks each including a plurality of pages. This is disclosed, for example, in JP-A-11-176177. Another technique has also been proposed, which makes use of more than one separation-use transistor to subdivide a block into a plurality of sub-blocks, each of which is for use as an erase unit. An example of this technique is found in JP-A-2000-222895.
In a scheme for performing data erasing on a per-page basis or in units of sub-blocks without modifying the cell array configuration of prior known NAND flash memories, erase stress or write stress may be applied to the memory cells of not-selected or “unselected” subblocks at the time of data writing. This in turn causes a problem that the number of data rewrite is limited.
On the contrary, the use of a scheme for disposing a separation-use transistor or transistors within a block makes it possible to reduce the erase stress and write stress of unselected blocks. However in order to mike sure that the subblock separation or isolation while suppressing the erase and write stresses, it is desired to offer an ability to adjust the threshold levels of such separation transistors to an optimal value.